This invention relates to coupling signals from one electronic device or circuit to another, and more particularly to coupling signals between electronic devices or circuits having different clock domains defined by respective clocks that may differ in phase from each other.
Many electronic devices operate in a synchronous manner in which the timing of signals in the device are controlled by a clock signal. The transitions of the clock signal occur at substantially the same time throughout the circuit, thereby ensuring that signals coupled or created responsive to the transitions of the clock signal are properly synchronized to each other.
Although synchronism between signals can be maintained when the same clock signal, or clock signals derived from the same clock signal, are used throughout a circuit. It is substantially more difficult to properly synchronize signals coupled from one electronic device to another when the electronic devices operate in different clock domains defined by respective clock signals having phases that may differ from each other in some unpredictable or uncontrolled manner.
One example of an electronic device in which signals must be coupled between circuits operating in different clock domains is a packetized dynamic random access memory (xe2x80x9cDRAMxe2x80x9d), using Synchronous Link DRAM (xe2x80x9cSLDRAMxe2x80x9d) architecture. An example of a SLDRAM is shown in FIG. 1. With reference to FIG. 1, the SLDRAM 16 includes a clock generator circuit 40 that receives a command clock signal CMDCLK and generates an internal clock signal ICLK, a data clock signal DCLK, a write clock signal WCLK, and a large number of other clock and timing signals to control the timing of various operations in the SLDRAM 16. The SLDRAM 16 also includes a command buffer 46 and an address capture circuit 48, which receive the internal clock signal ICLK, a command packet CA0-CA9 on a 10-bit command bus 50, and a FLAG signal on line 52. A memory controller (not shown) or other device normally transmits the command packet CA0-CA9 to the SLDRAM 16 in synchronism with the command clock signal CMDCLK. The command packet, which generally includes four 10-bit packet words, contains control and address information for each memory transfer. The FLAG signal identifies the start of a command packet, and it also signals the start of an initialization sequence. The command buffer 46 receives the command packet from the bus 50, and compares at least a portion of the command packet to identifying data from an ID register 56 to determine if the command packet is directed to the SLDRAM 16 or another SLDRAM 16. If the command buffer 46 determines that the command packet is directed to the SLDRAM 16, it then provides the command words to a command decoder and sequencer 60. The command decoder and sequencer 60 generates a large number of internal control signals to control the operation of the SLDRAM 16 during a memory transfer.
The phase of the ICLK signal relative to the CMDCLK signal is determined during an initialization procedure. As described more fully in U.S. patent application Ser. No. 08/890,055 to Baker et al, which is incorporated herein by reference, a memory controller (not shown) repeatedly applies packet words to the SLDRAM 16. The memory device attempts to capture these packet words in the command buffer 46 using a variety of different phases of the ICLK signal relative to the phase of the CMDCLK signal received from the memory controller. The memory device then determines which phase of the ICLK signal was best able to capture the packet words, and uses this phase during normal operation of the SLDRAM 16.
The address capture circuit 48 also receives the command words from the command bus 50 and outputs a 20-bit address corresponding to the address information in the command packet. The address is provided to an address sequencer 64, which generates a corresponding 3-bit bank address on bus 66, a 10-bit row address on bus 68, and a 7-bit column address on bus 70. The column address and row address are processed by column and row address paths 73, 75 as will be described below.
One of the problems of conventional DRAMs is their relatively low speed resulting from the time required to precharge and equilibrate circuitry in the DRAM array. The SLDRAM 16 shown in FIG. 1 largely avoids this problem by using a plurality of memory banks 80, in this case eight memory banks 80a-h. After a read from one bank 80a, the bank 80a can be precharged while the remaining banks 80b-h are being accessed. Each of the memory banks 80a-h receives a row address from a respective row latch/decoder/driver 82a-h. All of the row latch/decoder/drivers 82a-h receive the same row address from a predecoder 84 which, in turn, receives a row address from either a row address register 86, redundant row circuit 87, or a refresh counter 88 as determined by a multiplexer 90. However, only one of the row latch/decoder/drivers 82a-h is active at any one time as determined by bank control logic 94 as a function of a bank address from a bank address register 96.
The column address on bus 70 is applied to a column latch/decoder 100, which supplies I/O gating signals to an I/O gating circuit 102. The I/O gating circuit 102 interfaces with columns of the memory banks 80a-h through sense amplifiers 104. Data is coupled to or from the memory banks 80a-h through the sense amplifiers 104 and I/O gating circuit 102 and a data path subsystem 108, which includes a read data path 110 and a write data path 112. The read data path 110 includes a read latch 120 that stores data from the I/O gating circuit 102. In the SLDRAM 16 shown in FIG. 1, 64 bits of data are stored in the read latch 120. The read latch then provides four 16-bit data words to an output multiplexer 122 that sequentially supplies each of the 16-bit data words to a read FIFO buffer 124. Successive 16-bit data words are clocked into the read FIFO buffer 124 by the data clock signal DCLK generated by the clock generator circuit 40. As explained below, the DCLK signal is also coupled to the memory controller or other device that receives the data read from the SLDRAM 16.
The phase of the DCLK signal relative to the CMDCLK signal, like the phase of the ICLK signal, is determined during the initialization procedure. The memory controller (not shown) determines which phase of the DCLK signal will cause the DCLK signal as received by the memory controller to be in phase with the CMDCLK signal that the memory controller applies to the SLDRAM 16. The memory controller then applies a packet to the SLDRAM 16 that causes the clock generator 40 to use the selected phase of the DCLK signal during normal operation of the memory device. As a result, the memory controller can operate in a single clock domain regardless of which of several memory devices it is accessing.
The read FIFO buffer 124 operates in a clock domain corresponding to the DCLK signal. On the other hand, the command buffer 46, the command decoder and sequencer 60, and the memory arrays 80a-h operate in a clock domain corresponding to the ICLK signal. The phase of the DCLK signal relative to the phase of the ICLK signal selected during the initialization procedure will vary in an unpredictable and uncontrollable manner since they will depend upon such factors as signal path lengths and the operating speed of various circuits in the SLDRAM 16 and the memory controller. As a result, the read FIFO buffer 124 operates in a clock domain that is different from the clock domain in which the command buffer 46, the command decoder and sequencer 60, and the memory arrays 80a-h operate.
After each 16-bit word is clock into the read FIFO buffer 124, it is clocked out of the read FIFO buffer 124 by a RCLK clock signal obtained by coupling the DCLK signal through a programmable delay circuit 126. The programmable delay circuit 126 is also programmed during initialization of the memory device. In particular, the memory controller (not shown) programs the delay so that the data read from the SLDRAM 16 is received by the memory controller or other device with a phase at which the DCLK signal is best able to capture the read data at the memory controller. The procedure used is similar to the procedure described above for determining the phase of ICLK except that the determination of the optimum phase of RCLK is determined by the memory controller rather than by the SLDRAM 16.
The read FIFO buffer 124 sequentially applies the 16-bit words to a driver circuit 128 which, in turn, applies the 16-bit data words to a data bus 130 forming part of the processor bus 14. The driver circuit 128 also applies the data clock signal DCLK to a clock line 132 so that the memory controller (not shown) processor or other device reading data on the data bus 130 can be synchronized with the data.
The phase of the RCLK signal relative to the phase of the DCLK signal selected during the initialization procedure will also vary in an unpredictable and uncontrollable manner for the same reasons that the phase of the DCLK signal relative to the phase of the ICLK signal varies in an unpredictable and uncontrollable manner. As explained above, the data are clocked into the read FIFO buffer 124 by the DCLK signal, and a portion the circuitry (not shown) in the read FIFO buffer 124 that receives the data from the multiplexer thus operates in the clock domain of the DCLK signal. However, the portion the circuitry (not shown) in the read FIFO buffer 124 that applies the data to the driver circuit 128 operates in the clock domain of the RCLK signal. As a result, the read FIFO buffer 124 operates in two different clock domains, namely the clock domain of the DCLK signal and the clock domain of the RCLK signal.
The write data path 112 includes a receiver buffer 140 coupled to the data bus 130. The receiver buffer 140 sequentially applies 16-bit words from the data bus 130 to four input registers 142, each of which is selectively enabled by a signal from a clock generator circuit 144. The clock generator circuit generates these enable signals responsive to the data clock DCLK, which, for write operations, is applied to the SLDRAM 16 on line 132 from the memory controller or other device that applies the write data to the memory device.
As with the ICLK signal, the clock generator 144 is programmed during the initialization procedure so that the clock signal applied to the input registers 142 has a phase relative to the phase of the DCLK signal that is best able to clock the write data into the input registers 142. This procedure is similar to the initialization procedure described above for selecting the phase of the ICLK signal.
In operation, the input registers 142 sequentially store four 16-bit data words and combine them into one 64-bit data word applied to a write FIFO buffer 148. The write data are clocked into the write FIFO buffer 148 by a clock signal generated from the DCLK signal by the clock generator 144. The input registers 142 and the input portion of the write FIFO buffer 148 operate in the clock domain of the DCLK signal generated by the memory controller or other device. It should be noted that the write DCLK signal and the read DCLK signal are generated by different devices; the write DCLK signal is generated by the memory controller while the read DCLK signal is generated by the clock generator 40. As a result, the DCLK signal generated during a write operation establishes a clock domain that is different from the clock domain established by the DCLK signal generated during a read operation.
The data stored in the write FIFO buffer 148 are clocked into a write latch and driver 150 by a write clock WCLK signal to sequentially apply 64-bit write data to a write latch and driver 150. The write latch and driver 150 applies the 64-bit write data to one of the memory banks 80a-h through the I/O gating circuit 102 and the sense amplifiers 104. The WCLK signal is generated by the clock generator 40 to correspond to the timing at which the memory arrays 80a-h are able to receive the write data. The WCLK signal is thus in the clock domain of the ICLK signal, which is used to time the control signals generated by the command decoder and sequencer 60, as explained above. Thus, the write to data coupled through the write FIFO buffer 148 must also be coupled across two clock domains, namely the clock domain of the clock signal from the clock generator 144 and the clock domain of the ICLK signal.
The structure and operation of the SLDRAM 16 shown in FIG. 1 is shown and explained in greater detail in U.S. patent application Ser. No. 08/994,461 to Manning, which is incorporated herein by reference. As explained therein, one of the control signals generated in the clock domain of the ICLK signal is a STARTDCLK* signal that initiates the transfer of data to and from the SLDRAM 16. As explained further below, the read FIFO buffer 124 and the write FIFO buffer 148 respond to the STARTDCLK* signal to initiate the clock signal that couples data from the data bus 130 to the read FIFO buffer 124 and from the write FIFO buffer 148 to the data bus 130.
The problems encountered in coupling a signal from a portion of the SLDRAM 16 operating in one clock domain to a portion of the SLDRAM 16 operating in a second clock domain can be explained with reference to FIG. 2. The problem is initially explained with reference to crossing from the ICLK clock domain to the DCLK clock domain in the read FIFO buffer 124.
As shown in FIG. 2, four sets of data D0-D3 are clocked out of the latch 120 and coupled through the multiplexer 122 in synchronism with the ICLK signal. The data are clocked into the read FIFO offer 124 by the DCLK signal, as mentioned above. As shown in the third line of FIG. 2, the DCLK-A signal has a phase that lags the phase of the ICLK signal. The DCLK-A signal is thus able to accurately clock the data into the read FIFO buffer 124, as shown in the 4th line of FIG. 2.
The DCLK signal may alternatively have a phase that leads the phase of the ICLK signal, as shown by the signal DCLK-B in the 5th line of FIG. 2. Under these circumstances, the DCLK-B signal attempts to clock the first set of data D0 into the read FIFO buffer 124 at time t0, i.e., before the first set of data D0 have been coupled through the multiplexer 122. Furthermore, the DCLK-B signal becomes inactive before the fourth set of data D3 are coupled through the multiplexer 122. Therefore, the DCLK-B signal fails to clock the fourth set of data D3 into the read FIFO buffer 124.
A similar problem exists in the read FIFO buffer 122 when crossing from the clock domain established by the DCLK signal to the clock domain established by the RCLK signal. As illustrated FIG. 3, the DCLK signal is shown in the first line of FIG. 3 clocking four sets of data D0-D3 into the read FIFO buffer 124, as shown in the second line of the FIG. 3. The second and third lines of FIG. 3 show a read clock signal RCLK-A, which lags the DCLK signal, clocking the four sets of data D0-D3 out of the read clock buffer 124. As shown in the second and third lines of FIG. 3, the RCLK signal is able to properly clock the data D0-D3 out of the read FIFO buffer 124 when the RCLK signal lags the DCLK signal. However, when the RCLK signal leads the DCLK signal, as shown by the RCLK-B signal in the fifth line, the data cannot be properly clocked from the read FIFO buffer 124. Specifically, the RCLK-B signal attempts to clock the first set of data D0 out of the buffer 124 before the DCLK signal has clocked the data D0 into the buffer 124. Further, since the RCLK-B signal has become inactive by the time the fourth set of data D3 are clocked into the buffer 124, the fourth set of data D3 are never clocked out of the buffer 124.
A similar problem exists in the write FIFO buffer 148 when crossing from the clock domain established by the clock signal from the clock generator 144 to the clock domain established by the ICLK (WCLK) signal.
While the above problems could apparently be solved by preestablishing set phase relationships between the ICLK and the DCLK signals, between the DCLK and RCLK signals, and between the ICLK signal and the clock signal from the clock generator 144, doing so would preclude the phases of these signals from being properly adjusted during the above-described initialization procedures.
There is therefore a need to provide a method and apparatus that is capable of coupling signals between two or more clock domains. Although the problem is illustrated with respect to a packetized DRAM like the SLDRAM, the problem may also exist to varying degrees with other types of memory devices, such as synchronous DRAMs.
A method and apparatus for coupling data across first and second clock domains defined by respective first and second clock signals. A phase comparator receiving signals indicative of the relative phase of the first and second clock signals generates a phase signal indicative of whether or not the first clock signal leads the second clock signal. The phase signal is applied to a state machine that also receives either the first or second clock signal and a start signal signifying the start of coupling the data between the first and second clock domains. The state machine generates an output clock signal synchronized to the clock signal received by the state machine that is adapted to clock the data between the clock domains. The state machine is responsive to the phase signal to adjust the time period from the start signal to when the output clock signal is generated so that the time period is longer when the first clock signal leads the second clock signal than when the first clock signal does not lead the second clock signal.